American Megatrends, Inc.
Tech Tip #24.001
02/11/91

Problem:

Cyrix Fastmath EMC87 device does not work on Mark IV Screamer 33MHz
motherboard, with external cache enabled.


Solution:

The EMC87 device is compatible to 80387 coprocessor protocol and
executes reads and writes at zero wait states.
Weitek, also a memory mapped device, allows one wait state for 
read/write operations.
The areas where EMC87/Weitek devices are located must be
noncached, on Mark IV motherboard, the external cache is always
enabled, it is disabled when the cache logic determines that the
current access is to a noncached area.
Because of zero wait state restriction of EMC87, the point where
the EMC87 device samples data, the PD bus is driven by the external
cache.

This problem was temporarily solved by AMI by giving data to the
EMC87, at the point where to external cache is no longer valid.
PAL U39 has been changed from H10E2404 to H20E2404. This PAL has
not yet been released as an ECN.

Cyrix will most probably eliminate this problem by adding a 
wait state on read/write operations (like Weitek) in the next
silicon of EMC87 chip.