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DRIVE AN LCD WITHOUT ANY TRAINING

A new generation of VGA controllers eradicates the difficult task of
designing controllers to drive LCDs and other flat-panel displays.  These
innovative controllers can convert color to monochrome (gray scale) while
doing split-panel output-data formatting and control.

Architectural differences between typical VGA display monitors--analog color
CRTs--and typical LCD panels--640-by-480 pixel digital monochrome
displays--created the designing problems.  LCD panels are made in upper and
lower (split-level) sections, which offer a dual 4-bit data bus so the panel
can be refreshed at a higher frame rate for improved display contrast.  With
this approach, data must be sent to the upper- and lower-panel sections in
parallel, unlike a VGA monitor, which requires one pixel composed of three
analog signals: red, green, and blue.

The new VGA controllers perform the necessary gray-scale conversion by first
mapping the required color to the equivalent gray-scale value.  This value
then drives the logic that varies the ratio of "on" versus "of" pixels
displayed during multiple frame sequences.  The human eye, which integrates
the displayed data, perceives the desired intensity or gray scale.  Within
these devices, specialized sequencing logic reformats the data for output to
the upper and lower panels and supplies the necessary split-level control
signals.

For example, a VLSI chip set, such as the Cirrus Logic CL-GD620/610
CRT/Flat-Panel VGA controller, can handle these tasks.  Aimed at IBM
PC/AT-compatible laptop PCs, the CMOS chip set--which consists of a GD620 
sequence/CRT controller and a GD610 graphics/attributes device--is
compatible  with Intel 80X86 series microprocessors and 8-bit split panels
(4-bit upper and lower).  The chip set also supports the standard VGA
video-data output format for typical laptops, and will supply up to 32
shades of gray in VGA color-graphics Mode 13 (with 320 horizontal by 200
vertical pixels, double scanned to fill 640 by 400 line panels).

The GD620/610 maintains complete backwards compatibility with all existing
IBM graphics software standards, such as EGA, CGA, MDA, and the Hercules
standard.  It's also hardware-compatible with analog and digital CRT
monitors and plasma and electroluminescent panels.  To simplify interfacing
with the many available LCD panels, the chip set comes equipped with 64
extension registers.  Using these registers, vendor-specific control
parameters can be loaded to configure the display panel.

A VGA subsystem built around the GD620/610 contains the controller chip set,
two 74HCT245 data-bus transceivers, a video memory-address decoder
(typically derived from existing motherboard logic), a 27C512 64-kbyte BIOS
ROM, eight 44C256 or 44C64 dynamic RAMs (DRAMs) for 1 Mbyte or 256 kbytes of
video memory, a 44C64 DRAM (for output data buffering), a CMOS RAMD AC for
the VGA analog monitor option, and four 74HCT244 buffers--two for address
buffering and two for LCD and CRT control-signal buffering (Fig. 1).

The GD620/610 chip set directly supports a 16-bit host-to-video-memory
interface and an 8-bit interface from the host to the BIOS ROM and the chip
set's internal registers.  The set can also be configured for a 16-bit BIOS
ROM interface through external logic.

To support a 16-bit data bus, the two 8-bit transceivers must connect the
16-bit host Data Bus signals (SD.sub.0-15.) to the GD620-610 multiplexed
Address/Data Bus (AD.sub.0-15).  The low-and high-order transceivers are
enabled by DSELL and DSELH, respectively.  Both devices' direction controls
are given by a DIR signal, which is sent low during read cycles.  The host
CPU can access 16 bits (two bytes) of video memory in one cycle, but all I/O
accesses to GD620/610 registers are limited to 8-bits per cycle.

The active high Chip Select (CS) must be asserted during I/O accesses to
video memory or BIOS, located between address A0000 and C7FFF.  This can be
done by decoding addresses LA.sub.19-23 with a 74HCT138 decoder chip and one
74HCT04 inverter, or similar decoding logic if -- MEMW and -MEMR from the AT
bus are used.  CS may be connected directly to SA.sub.19 if --SMEMW and
--MEMR are used and are active during low 1-Mbyte system memory-address
space.

Bus Control signal --SBHE can connect directly to the GD620's control
signal, SBHE, to supply 16-bit I/O control.  The GD620 will only assert
MCS.sub.16 (memory chip select) in response to a 16-bit video-memory read or
write if it was programmed to do so.  Otherwise, it will respond to system
signals --SBHE and SA.sub.0 to steer the appropriate byte to the high-order
data bus during memory read or write cycles.  The bus-control signals --MEMW
and --MEMR (AT) or --SMEMW and --SMEMR (XT) can be used for memory read and
write control.

If 8-bit PC XT and 16-bit PC AT I/O bus operation is desired, such as for an
add-in board designed for VGA CRT-only operation, designers may wish to add
logic to detect the presence of ground on the AT's extension connector pin
(available on I/O bus-extension connectors J.sub.C and J.sub.D.  Then the
SBHE and CS inputs can be driven according to the size of the I/O data bus
that the board is connected to.

For example, an 8-bit PC XT slot wouldn't see the ground signal, so the
logic would connect SA.sub.19 to CS and pull SBHE high.  When the board is
installed in a 16-bit slot, the grounded extension connectors would be
detected and the logic would decode LA.sub.19-23 to drive the CS input. 
SBHE is then passed through to the GD620.  All other host-system control
signals are connected, as in the 8-bit implementation.

BIOS INTERFACE

It's possible for the chip set to support a 16-bit VGA BIOS interface if
more logic is added to decode the unlatched system address lines
(LA.sub.19-23.) and assert --MCS.sub.16 when the BIOS program memory area is
accessed.  Extreme caution must be exercised to generate --MCS.sub.16
because it must be asserted right after decoding a valid BIOS address but
before the AT bus-control signal BALE (buffered address latch enable) falls.
A "--B" speed PAL device, such as a 20L8-B, can be used because of its 15-ns
response.

Because the GD620 will assert MCS.sub.16 during a video-memory access, the
logic that generates --MCS.sub.16 for 16-bit BIOS accesses must be ORed with
the MCS.sub.16 output.  To avoid interference with the MCS.sub.16
signal,--MCS.sub.16 can be three-stated when the system doesn't access the
16-bit BIOS.  The BIOS ROMs can be programmed to split the data between odd
and even ROM devices, or designers can opt to use two identical 8-bit BIOS
ROMs by grounding the even ROM's A.sub.0 input and pulling the odd ROM's
A.sub.0 input high.

The GD620/610 chip set supports the standard VGA 256-kbyte or 1-Mbyte
video-memory interface.  The additional memory, utilized for "pop-up" menus
in windowing applications and multiple pages that are used in animation, can
be accessed by programming GD620/610 extension registers.

Because independent host-CPU access versus CRT display-refresh access is
supported, the host can access the additional memory for general-purpose
storage.  The CPU/CRT interleave configuration, however, will limit the
host-access bandwidth.

MEMORY ARCHITECTURE

The DRAM video-memory architecture supports a 32-bit, nonmultiplexed,
bidirectional memory data bus, organized as four pages of four planes (Fig.
2).  The 32-bit, video-memory data bus is organized as four 8-bit buses,
M0-D.sub.0-7., M1-D.sub.0-7., M2-D.sub.0-7., and M3-D.sub.0-7.  These 32
pins all connect to the GD610 Graphics/attributes controller chip. 
M0-D.sub.0-7 also connects to both the GD620 and the GD610.

The GD620 contains two 9-bit DRAM address buses, AA.sub.0-8 and AB.sub.0-8.,
to address the individual planes.  The AA bus connects to planes 0 and 1 and
the AB bus connects to 2 and 3.  AA.sub.8 and AB.sub.8 aren't used in the
standard 256-kbyte configuration.  The GD620 supplies one DRAM Write Enable
signal (WE) and one Column Address Strobe signal (CAS).  Four Row Address
Strobe signals, RAS.sub.0., RAS.sub.1., RAS.sub.2., and RAS.sub.3 make it
possible for individual or common-memory plane selection.

The DRAM Output-Enable signals (-OE) aren't driven by the GD620/610 and
should be connected to ground.  DRAM refresh is performed automatically by
the chip set and occurs three to five times per scanline, which satisfies
the refresh requirements for 256-kbit or 1-Mbit DRAMs.

FRAME ACCELERATION

The frame-accelerator DRAM interface helps users to save power by driving a
panel at lower data rates as the same contrast is maintained.  Users can
also drive a panel at a higher rate to obtain even more contrast.  To supply
gray-scale conversion and support for split-panel/dual-drive LCD
flat-panels, an extra 64-kbyte by 4-bit DRAM device is required.  A
256-kbyte by 4-bit DRAM could be used if the high-order address input,
A.sub.8., is grounded.  The frame accelerator also reformats the video data
for parallel output to the LCD's 4-bit upper and lower-panel data buses.

The frame-accelerator DRAM connects to the GD610 graphics/attributes
controller chip, which serves as the DRAM address/control supplier.  The
4-bit frame data bus is multiplexed with the low-order Frame Address signals
(FR-AD.sub.0-3.).  The high-order Frame Address signals (FR-A.sub.4-7.)
connect to the four DRAM address inputs A.sub.4-7.  DRAM control is given by
FRWE, FRCAS, FRRAS, and FROE.  The required DRAM maximum access time (Taa)
is 100 or 200 ns.

VIDEO-CLOCK INTERFACE

The GD620/610 supports eight external video clocks that are selected as
required for each video mode.  The current maximum video clock-rate
supported is 33 MHz.  The GD620 has three bidirectional clock I/O control
lines--CLK.sub.32., CLK.sub.28., and CLK.sub.25.--and each can be programmed
either as inputs from crystal-oscillator modules or as outputs to drive one
of eight clock multiplexers or a phase-locked-loop generator.

If the signals are used as outputs, the selected frequency should be applied
to the OSC clock input to supply 28.322, 25.172, 16.257, and 14.318 MHz for
compatibility with the VGA and previous IBM video-adaptor standards such as
EGA, CGA, and MDA.  For Cirrus Logic's enhanced resolution modes, such as
800 by 600 by 16 colors, a 32.514 MHz frequency is required.  Thse modes
also need a CRT monitor that can display higher resolution and frequencies. 
The 16.257-MHz frequency is produced internally in the GD620 by dividing the
external 32.514 MHz by two.

Typically, split-screen VGA-compatible LCD panels require two parallel 4-bit
data transfers--one each for the upper and lower panels at data rates from 3
to 6 MHz.  For those applications, the GD620 will need an external clock
source (12 to 24 MHz) applied to its external clock (CKEXT) input.

DIGITAL MONITORS

The GD620/610 supports standard RGBI and RGB TTL digital CRT monitors
compatible with IBM's monochrome, enhanced, and standard color displays. 
The digital multifrequency monitors, such as the NEC Multisync, Sony
Multiscan, Taxan Multivision, and Mitsubishi Diamondscan also are supported.
IBM's PS/2 monitors won't accept digital RGBI video signals.  The GD620/610
TTL video/sync outputs should be buffered with 74HTC244 drivers due to the
high drive requirements of the attached monitor and cable assembly.  Ferrite
beads and small capacitors can be added in series with the TTL Video/Sync
Output signals to reduce rfi.

To support the IBM PS/2 monitor, it's necessary to connect the GD620/610 to
a triple 6-bit RAMDAC that contains a 256-kbyte-by-18-bit dual-port RAM,
such as the BT-471 or INMOS-171 (Fig. 3).  The RAMDAC will output
PS/2-compatible video signals essential for analog, PS/2, and multifrequency
monitors.

The PS/2 monitor requires the standard TTL Digital Sync signals, HSYNC and
VSYNC, which should be buffered with 74HCT244 drivers.  Users must supply
support for RAMDAC overlay palette registers that superimpose grids, menus,
and so forth, with VGA video.  This feature isn't supported by the IBM VGA
video standard.

Some multifrequency monitors can work with analog or digital inputs that
makes them PS/2-monitor clones.  Typically, these monitors have a
digital/analog select switch and one input connector that needs a special
conversion cable.

The RAMDAC's palette RAM is a dual-port device that can be accessed by the
host CPU system and the GD610 video-data output bus.  This enables
application programs to read to or write from the palette RAM from one port
as the GD610 supplies video data to the other.  By changing the palette
RAM's RGB data values, several interesting animation programs can be
created.

CONNECTING THE OUTPUTS

The GD610 has eight TTL digital video outputs, P.sub.0-7., which connect
directly to the RAMDAC's 8-bit video pixel port (Fig. 3, again).  This port
gives the address for the RAMDAC's internal palette RAM during display
cycles.  The palette RAM sends 18-bits of data for the three internal 6-bit
d-a converters.

The converters supply the PS/2 monitor with the three RGB analog color/mono
video signals.  The 18-bits of RAM make up a palette of 256 kcolors while
the 8-bit pixel-port address can display 256 colors at once.

The RAMDAC host data port is an 8-bit bidirectional bus that connects to the
GD620/610's multiplexed address/data bus.  Two RAMDAC address inputs,
A.sub.0 and A.sub.1., connect directly to Host-Address Bus signals, SA.sub.0
and SA.sub.1., and select the data's source or destination.

The RAMDAC's internal 8-bit address register indexes the palette RAM.  The
GD620 decodes I/O port addresses 3C.sub.6 through 3C.sub.9 and asserts the
color palette Read and Write Strobes, CPRD and CPWR, timed with-SIOR and
-SIOW.

The GD620/610 video-blanking signal, Blank, must be connected to the
RAMDAC's -Blank input.  Also, the RAMDAC will need external analog
components to supply the mandatory reference voltages or currents to adjust
the analog video-output levels.  The desired resistive loads of 37.5 or 75
[omega] now can be met.  The RAMDAC manufacturer's data sheets can give
specific voltage or current reference and load requirements.

SPLIT-SCREEN LCDS

The chip set interfaces directly with LCDs manufactured in two sections,
which are connected in the middle of the screen (Fig. 4).  Split-screen LCD
panels are typically manufactured as two 640-by-240 sections to deliver a
640-by-480 VGA-compatible screen.  The split-panel design allows for a
higher refresh rate, which produces better contrast.  This results from data
that's supplied to the upper- and lower-panel sections in parallel, 4 bits
to each section.  The scenario differs from CRT monitors that serially
receive the video data.

In addition, the display timing of LCD panels is different from CRT timing. 
The GD620/610 has internal extension registers used specifically for LCD
timing and display formatting.  The chip set sends the essential LCD control
signals to connect to dual 4-bit split-screen LCD modules.  The GD620/610
also may be interfaced to single-drive-LCD, plasma, and electroluminescent
panels.  In this case, the frame accelerator is still needed for gray-scale
display.

Because LCD panels are digital-monochrome devices, the GD620/610 must
convert VGA color video into the equivalent gray-scale video value.  This is
handled by proprietary intelligent color-to-gray-scale mapping and
frame-rate modulation techniques.  The chip set contains an internal
color-mapping RAM that shadows the VGA RAMDAC.  Applications programs that
write to the RAMDAC will automatically update the internal mapping RAM,
which will then drive the internal-conversion logic.

Once the color is mapped to the equivalent gray-scale value, the GD620/610
will determine the panel's intensity by alternating the data patterns
transferred during multiple-frame sequences.  The data patterns contain
varied on-versus-off pixel ratios to achieve the gray scale.  The data
patterns are also varied to eliminate unwanted frequencies that might
produce noise and interference.

The frame accelerator makes it possible for the chip set to drive LCD panels
at higher frame rates than CRT monitors.  This higher rate eliminates
flicker and noise problems and increases panel-display contrast.  The
accelerator also reformats the video-output data for parallel, upper- and
lower-panel data transfer.

The GD610 produces a Video Data Clock signal (VDCLK), a Frame Start signal
(LFS), a Line Sync signal (LLCLK), and an ac Modulation signal (MOD).  These
must all be buffered with 74HCT244 or similar drivers before connecting to
the panel.  The GD610 also adds a dual 4-bit data bus using the video-data
output bus.  P.sub.4-7 connect to the upper-panel data bus as P.sub.0-3
connect to the lower-panel data bus.  The bus should also be buffered with a
74HCT244 or similar driver because of the data bus' high drive and
capacitive loading.

The GD620/10 may be utilized with single screen 640-by-200 or -by-240 panels
that have a 4-bit data bus, but aren't VGA compatible.  The half-frame
buffer is used for gray-scale in this case.

PLASMA-PANEL INTERFACE

The GD620/610 can support 640-by-400 or -by-480 single-screen plasma panels
by adding a pipeline register and several delay buffers (Fig. 5).  These
extra parts match the data set-up- and hold-time requirements of the plasma
panel.  But the chip set won't supply direct gray-scale support for these
panels.  The chip set does offer intelligent color-to-monochrome mapping and
it outputs a 4-bit gray-scale value.  This value can drive plasma panels
containing internal pulse-width-modulation circuitry that performs 16-level
gray-scale conversion.  The panels typically require the normal Video Data
and Sync signals and a video-data clock.

Designers should use a 74HCT374 register to latch the 4-bit video data and
the HSYNC and VSYNC on the rising edge of VDCLK so the register outputs can
drive the panel.  To allow for panel-data setup time, VDCLK should be
delayed with 74HCT244-type buffers, then applied to the panel.  The
panel-data transfer sequence occurs in parallel with the pipelined data from
the GD610.  Check the plasma panel manufacturers data sheet for the specific
timing and signal-level requirements.

The GD620/610 can read the values of 16 switches (or jumpers) that supply
the chip-set configuration parameters.  In addition, three PS/2-monitor
control lines can be sensed by the chip set to obtain information about the
monitor type.

Eight configuration switches and three monitor-detect lines connect to the
GD620/610's multiplexed address/data bus, with 4.7- and 10-k[omega]
resistors.  This is needed to isolate the switches from the multiplexed
address/data bus during the normal bus activity.  The values of these
switches are read during power-up or reset sequencing and are stored in the
chip set for configuration control.  Refer to the GD620/610 technical
reference manual for specific switch configurations.

AUXILIARY INTERFACES

The GD620/610 was primarily designed for motherboards in laptop or portable
PCs that don't require a VGA feature connector.  This connector is normally
supported on add-in VGA video boards so an external video source, such as a
graphics coprocessor, can drive the RAMDAC and attached VGA monitor. 
Designers may choose to add this feature if the GD620/610 is used in a VGA
add-in board design.

Because the GD620/610 is a VGA controller chip set, interchip
synchronization and communication is available with ten control signals:
ITS, Latch, CPUCYC, S/L, MCLK, VSYNC, Blank, Cursor, DE, and CGSEL.  The
timing relationship between these signals require extra care when connecting
them to additional loads that may offset their timing.

Two programmable output lines, FC.sub.0 and FC.sub.1., can be used to
control an LCD backlight switch.  This power-down control can be used to
switch off the clock except when applications programs try to communication
with the RAMDAC.  Further conserving power, the DRAM can be powered down to
only refresh cycles.

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