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80486VESA
FREE COMPUTER TECHNOLOGY, INC.
80486VESA
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Processor
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80486SX/80487SX/80486SX2/80486DX
ODP486/80486DX2/Pentium Overdrive
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Processor Speed
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20/25/33/40/50(internal)/66(internal)MHz
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Chip Set
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SiS
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Max. Onboard DRAM
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32MB
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Cache
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64/128/256KB
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BIOS
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AMI
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Dimensions
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330mm x 218mm
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I/O Options
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32-bit VESA local bus slots (3)
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NPU Options
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None
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CONNECTIONS
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Purpose
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Location
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Purpose
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Location
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External battery
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JP1
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Reset switch
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JP17
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Peripheral power save
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JP2 & JP3
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Turbo LED
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JP18
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Speaker
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JP15
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Turbo switch
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JP19
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Power LED & keylock
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JP16
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32-bit VESA Local bus slots
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SL1, SL2,SL3
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USER CONFIGURABLE SETTINGS
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Function
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Jumper
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Position
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»
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CMOS normal operation
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JP21
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pins 2 & 3 closed
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CMOS memory clear
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JP21
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pins 1 & 2 closed
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DRAM CONFIGURATION
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Size
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Bank 0
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Bank 1
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1MB
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(4) 256K x 9
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NONE
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2MB
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(4) 256K x 9
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(4) 256K x 9
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4MB
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(4) 1M x 9
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NONE
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8MB
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(4) 1M x 9
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(4) 1M x 9
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16MB
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(4) 4M x 9
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NONE
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20MB
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(4) 1M x 9
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(4) 4M x 9
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32MB
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(4) 4M x 9
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(4) 4M x 9
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CACHE CONFIGURATION
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Size
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Bank 0
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Bank 1
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TAG
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64KB
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(4) 8K x 8
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(4) 8K x 8
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(1) 8K x 8
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128KB
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(4) 32K x 8
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NONE
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(1) 8K x 8
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256KB
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(4) 32K x 8
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(4) 32K x 8
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(1) 32K x 8
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CACHE JUMPER CONFIGURATION
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Size
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JP11
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JP12
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64KB
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Open
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Open
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128KB
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pins 1 & 2 closed
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Closed
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256KB
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pins 2 & 3 closed
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Closed
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CPU TYPE CONFIGURATION
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CPU Type
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JP7
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JP8
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80486SX
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pins 2 & 3 closed
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Open
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80487SX
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pins 1 & 2, 3 & 4 closed
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pins 2 & 3 closed
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80486SX2
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pins 1 & 2, 3 & 4 closed
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pins 2 & 3 closed
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80486DX
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pins 1 & 2, 3 & 4 closed
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pins 1 & 2 closed
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80486DX2
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pins 1 & 2, 3 & 4 closed
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pins 1 & 2 closed
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ODP486 (168-pin)
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pins 1 & 2, 3 & 4 closed
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pins 1 & 2 closed
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ODP486 (169-pin)
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pins 1 & 2, 3 & 4 closed
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pins 2 & 3 closed
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Pentium Overdrive
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pins 1 & 2, 3 & 4 closed
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pins 2 & 3 closed
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CPU CLOCK CONFIGURATION
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CPU Clock
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JP4
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JP5
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JP6
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20MHz
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Closed
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Closed
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Open
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25MHz
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Closed
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Open
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Closed
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33MHz
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Open
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Closed
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Closed
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40MHz
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Closed
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Open
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Open
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50MHz
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Open
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Closed
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Open
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VESA WAIT STATE/BUS SPEED CONFIGURATION
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CPU speed
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Wait states
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JP13
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JP14
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<= 33MHz
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0 wait states
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Open
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Open
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> 33MHz
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1 wait state
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Closed
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Closed
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MISCELLANEOUS TECHNICAL NOTE
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Note: JP2 & JP3 are used for an optional peripheral card timed power shut-down that is set up in CMOS.
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